The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly as device characteristic dimensions are scaled down to 65 nm and below.
In particular, in forming dual damascenes, processing difficulties arise as device sizes are scaled down. For example as device sizes are scaled down, the behavior of conventional materials in forming hardmasks, anti-reflectance coatings (ARC), and via plugs is critical due to the small process windows as small device dimensions shrink. In addition, defects such as residual material or undesirable etching profiles are magnified in a relative sense with respect to smaller device dimensions.
There are in general two dual Damascene processes commonly practiced in the prior art. One process is typically referred to as a via-first process whereby the via is first patterned and etched through an inter-metal dielectric (i.e. IMD) layer, followed by etching an overlying trench portion. The via first process requires two photolithographic patterning steps for separately forming the via and the trench portions. One main problem in the via first process is commonly known as the “via poison” problem which includes photo-resist interaction and etching damage to the via sidewalls during trench etching. To overcome this problem, prior art processes have proposed several different methods for filling the via with a protective resin material to form a via plug prior to trench etching to protect the via sidewalls. The resin materials is also carefully selected for minimum interaction with the via sidewall, and to improve the trench etching profile. However, the use of resinous via plugs has been found to cause new problems that become more pronounced as trench dimensions are scaled down. For example, new low-k materials used as IMD can cause difficulty in removing via plug material following trench etching as a result of small via size, interaction of resin with new low-k IMD, materials, especially organic based low-k materials, and/or interfering with etching profiles during trench etching. In addition, the resinous via plug materials contaminate etching chambers which can cause increasingly detrimental defects at smaller characteristic device dimensions.
Another approach to forming dual damascenes is referred to as the self aligned dual damascene formation process based on dual hard-mask layers over IMD, where the trench is first patterned over the first hard mask layer, followed by patterning and etching vias over the second hard-mask layer within the patterned trench area, and then followed by simultaneously etching the IMD layer through both the overlying trench and the vias using both hard masks as etching masks during etching IMD. One key to successfully carrying out the self aligned dual damascene formation process is the hardmask material used for patterning the trench. For example, typically CVD nitride is used as one of the materials for the hardmask, which can interact with DUV photoresist during lithographic processes and lead to residual polymeric etching contaminants referred to as photo-resist poisoning. Such residual polymeric defects are difficult to remove and may degrade a wiring electrical resistance or otherwise interfere with a metal filling process thereby degrading device performance and reliability. In addition, such photoresist poisoning also leads to unacceptable contaminant levels in etching reactor chambers, which further leads to unacceptable particulate contamination of the wafer in an etching process.
There is therefore a need in the large scale integrated circuit processing art to develop improved dual damascene manufacturing processes which avoid the various drawbacks of the prior art including improved via protection methods and improved hardmask and ARC formation methods to avoid the various problems of the prior art as well as improve a process flow thereby improving device performance, reliability, and throughput.
It is therefore an object of the invention to provide improved dual damascene manufacturing processes which avoid the various drawbacks of the prior art including improved via protection methods and improved hardmask and ARC formation methods to avoid the various problems of the prior art as well as improve a process flow thereby improving device performance, reliability, and throughput, in addition to overcoming other shortcomings and deficiencies in the prior art.